1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise highly capacitive gate structures including a metal-containing electrode and a high-k gate dielectric of increased permittivity compared to gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may no longer be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since, typically, a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain the high drive currents, commonly, the controllability of the respective channel requires pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll-off, and also reducing significant variations of transistor performance with a variation in gate length. Since the threshold voltage of the transistors is significantly determined by the work function of the gate material that is in contact with the gate dielectric material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride, aluminum oxide and the like, may frequently be used, wherein the corresponding work function may be adjusted so as to be appropriate for one type of transistor, such as N-channel transistors, while P-channel transistors may require a different work function and thus a differently treated titanium nitride material or any other appropriate metal-containing material in order to obtain the desired threshold voltage. In this case, complex and sophisticated manufacturing regimes may be required to provide different gate electrode materials in order to comply with the requirements of different transistor types. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique, which may also represent an additional complex process step, which, however, may provide reduced overall process complexity compared to the provision of the different metal-containing gate electrode materials or which may provide increased flexibility in obtaining appropriate transistor characteristics.
The adjustment of the band gap and thus of the threshold of sophisticated transistor elements on the basis of an appropriately selected semiconductor alloy, such as silicon/germanium, is a promising approach for sophisticated transistor elements comprising a metal gate, wherein, however, the presence of the threshold adjusting semiconductor alloy may interfere with other mechanisms for enhancing transistor performance. It is well known that switching speed and drive current capability of silicon-based field effect transistors may be increased by modifying the lattice structure in the channel region of the transistor. That is, by creating compressive or tensile strain in the channel region of the transistor, the charge carrier mobility may be increased, thereby achieving the desired increase of transistor performance. For example, a compressive strain component induced along the current flow direction of a P-channel transistor for a standard crystallographic configuration of the silicon region, i.e., a (100) surface orientation of the silicon material with the current flow direction being aligned along a (110) crystallographic axis, may provide a significant increase of the hole mobility. On the other hand, a tensile strain component in the channel region of an N-channel transistor may increase electron mobility. On the other hand, a tensile strain component in a P-channel transistor may result in a reduction of charge carrier mobility, thereby negatively affecting the transistor characteristics. Consequently, the incorporation of a threshold adjusting semiconductor alloy in the channel region adjacent to the gate dielectric material may thus result in a modification of the lattice structure, which in turn may influence the overall transistor characteristics. In the case of a P-channel transistor, the presence of the silicon/germanium alloy at the interface between the gate dielectric material and the channel of the transistor may provide an efficient mechanism for appropriately positioning the valence band with respect to the work function of the metal electrode material, however, at the same time the silicon/germanium alloy may modify the lattice structure within the channel region. The silicon/germanium material has a natural lattice constant, that is, a lattice constant when provided in a substantially stress-free manner, that is greater than the natural lattice constant of silicon. Consequently, upon forming a crystalline silicon/germanium alloy on a silicon template material a corresponding lattice mismatch may result in the corresponding “distortion” of the silicon/germanium lattice and the silicon lattice adjacent to the silicon/germanium material. Thus, a corresponding lattice distortion may result in a tensile strain in the silicon material, thereby reducing the hole mobility as discussed above. Furthermore, this tensile strain component may be superimposed on a corresponding compressive strain component provided by other strain-inducing mechanisms, such as a strain created by a silicon/germanium alloy which may be locally provided in the drain and source areas. Furthermore, other strain-inducing mechanisms may typically be applied, for instance by forming highly-stressed dielectric materials above the basic transistor structure, so that the efficiency of these mechanisms may also be reduced due to the presence of the threshold-adjusting material in the channel region.
As a consequence, since threshold adjusting by providing a silicon/germanium alloy in the channel region of P-channel transistors for appropriate adaptation to the work function of a metal electrode material, as well as increasing transistor performance by providing a compressive strain component in the channel region, are individually very promising and efficient strategies, a combination without significant loss of efficiency of at least one of these mechanisms may be difficult on the basis of conventional process regimes.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.